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PIC16F946
DS41265A-page 188
Preliminary
2005 Microchip Technology Inc.
15.3.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
Set the PWM period by writing to the PR2
register.
2.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3.
Make the RC5/T1CKI/CCP1/SEG10 pin an
output by clearing the TRISC<5> bit.
4.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5.
Configure the CCP1 module for PWM operation.
TABLE 15-1:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
TABLE 15-2:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12kHz
156.3 kHz
208.3 kHz
Timer Prescaler (1, 4, 16)
16
4
1
PR2 Value
0xFFh
0x3Fh
0x1Fh
0x17h
Maximum Resolution (bits)
10
8
7
5.5
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
0Bh,8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0Ch
PIR1
EEIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0Dh
PIR2
OSFIF
C2IF
C1IF
LCDIF
—
LVDIF
—
CCP2IF
0000 -0-0
8Ch
PIE1
EEIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
8Dh
PIE2
OSFIE
C2IE
C1IE
LCDIE
—
LVDIE
—
CCP2IE
0000 -0-0
87h
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
10h
T1CON
T1GINV
T1GE
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 uuuu uuuu
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
xxxx xxxx
uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx
uuuu uuuu
17h
CCP1CON
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0 --00 0000 --00 0000
1Bh
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
xxxx xxxx
uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx
uuuu uuuu
1Dh
CCP2CON
—
CCP2X
CCP2Y
CCP2M3
CCP2M2
CCP2M1
CCP2M0 --00 0000 --00 0000
Legend:
x
= unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
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相关PDF资料
2-1546217-0 TERM BLK RCPT 20POS SIDE 5.08MM
1-1546217-9 TERM BLK RCPT 19POS SIDE 5.08MM
1-1546217-8 TERM BLK RCPT 18POS SIDE 5.08MM
1-1546217-7 TERM BLK RCPT 17POS SIDE 5.08MM
1-1546217-6 TERM BLK RCPT 16POS SIDE 5.08MM
1-1546217-5 TERM BLK RCPT 15POS SIDE 5.08MM
1-1546217-4 TERM BLK RCPT 14POS SIDE 5.08MM
1-1546217-3 TERM BLK RCPT 13POS SIDE 5.08MM
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